With the growing consumer demand for the high-resolution, low-noise digital imaging applications, CMOS image sensor manufacturers have been devoting themselves to the innovation in analog-to-digital conversion techniques such as multi-sampling techniques including multiple sampling of an input signal, analog-to-digital conversion, and averaging.
There is a trade-off relationship between the operating speed and power consumption of CMOS image sensors. In this regard, a 142366299.2 column-parallel structure is an optimal structure. However, there is a difficulty in integrating a readout circuit such as an analog-to-digital converter (ADC) into a narrow pixel width, Thus, a simple single-slope ADC is widely used in the column-parallel structure.
When a single-slope ADC uses a continuous time signal, optimal performance can be realized. However, if the continuous time signal becomes a discrete time signal in the middle of the analog-to-digital conversion, unwanted noise can be generated due to the coupling between adjacent columns. As the incident amount of light increases, shot noise becomes dominant in a high illumination period. Therefore, it is important to reduce noise in a low illumination period.
Various techniques are currently being studied to reduce such noise including determining a low illumination period and a high illumination period in advance to operate the CMOS image sensor in a high resolution mode during the low illumination period, changing a slope of a ramp signal, giving a time difference for the ramp signal to sample pixel signals multiple times, and making the ramp signal cross the pixel signal again, when a comparator determines that the pixel signal has crossed the ramp signal, by applying an offset to an input or output of the comparator.